Survey on Hardware Implementation of Montgomery Modular

Pratibha, K and Muthaiah, Rajappa Survey on Hardware Implementation of Montgomery Modular. International Journal of Pure and Applied Mathematics, 2018, vol. 119, n. 12, pp. 13437-13452. [Journal article (Paginated)]

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English abstract

This paper gives the information regarding different methodology for modular multiplication with the modification of Montgomery algorithm. Montgomery multiplier proved to be more efficient multiplier which replaces division by the modulus with series of shifting by a number and an adder block. For larger number of bits, Modular multiplication takes more time to compute and also takes more area of the chip. Different methods ensure more speed and less chip size of the system. The speed of the multiplier is decided by the multiplier. Here three modified Montgomery algorithm discussed with their output compared with each other. The three methods are Iterative architecture, Montgomery multiplier for faster Cryptography and Vedic multipliers used in Montgomery algorithm for multiplication.Here three boards have been used for the analysis and they are Altera DE2-70, FPGA board Virtex 6 and Kintex 7.

Item type: Journal article (Paginated)
Keywords: Montgomery algorithm, Modular multiplication (MM), Montgomery Modular Multiplication (MMM), Cryptography, Cryptography, cryptosystem, Urdhawa Tiryagbhayam Sutra and Montgomery Core
Subjects: B. Information use and sociology of information
B. Information use and sociology of information > BC. Information in society.
Depositing user: Raster Daster
Date deposited: 02 Aug 2018 07:27
Last modified: 02 Aug 2018 07:27
URI: http://hdl.handle.net/10760/33257

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